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BU9832GUL-W (8Kbit)
4. Status register write / read command
CS
Datasheet
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
bit 7
bit 6
bit 5
bi t4
bit 3
bit 2
bit 1
bit 0
SI
0
0
0
0
0
0
0
1
WP E N
＊
＊
＊
BP1
BP0
＊
＊
SO
High-Z
＊ =Don't care
Figure 37. Status register write command
Write status register command can write status register data. The data can be written by this command are 2 bits * 1 , that
is, BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be set .
As for this command, set CS LOW, and input ope code of write status register, and input data. Then, by making CS
HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CS rise, start CS after taking
the last data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is
determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array.
(Refer to the write disable block setting table.) To the write disabled block, write cannot be made, and only read can be
made.
CS
*1
3bits including 1WPEN (bit7)
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SI
SO
0
High-Z
0
0
0
0
1
0
1
bit7
WPEN
bit6
0
bit5
0
bit4
0
bit3
bit2
BP1 BP0
bit1
bit0
WEN R/B
Figure 38. Status register read command
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TSZ02201-0R2R0G100410-1-2
30.AUG.2012 Rev.001
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